set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]
set_property PACKAGE_PIN R4 [get_ports sys_clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
set_property PACKAGE_PIN U2 [get_ports rst_n]

# pcl7152
# set_property PACKAGE_PIN Y7 [get_ports {pixel_so_in[0]}]
# set_property PACKAGE_PIN AA8 [get_ports {pixel_so_in[1]}]
# set_property PACKAGE_PIN AB6 [get_ports {pixel_so_in[2]}]
# set_property PACKAGE_PIN AB7 [get_ports {pixel_so_in[3]}]
# set_property PACKAGE_PIN V8 [get_ports {pixel_so_in[4]}]
# set_property PACKAGE_PIN W9 [get_ports {pixel_so_in[5]}]
# set_property PACKAGE_PIN N13 [get_ports {pixel_so_in[6]}]
# set_property PACKAGE_PIN P14 [get_ports {pixel_so_in[7]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[7]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[6]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[5]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[4]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[3]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[2]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[1]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[0]}]
# set_property PACKAGE_PIN R16 [get_ports CLK_OUT]
# set_property PACKAGE_PIN R14 [get_ports CHIP_EN]
# set_property PACKAGE_PIN N14 [get_ports INT]
# set_property PACKAGE_PIN V9 [get_ports CI_CTRL]
# set_property PACKAGE_PIN Y9 [get_ports TRIGGER]
# set_property PACKAGE_PIN U7 [get_ports CLK_TX]
# set_property PACKAGE_PIN V7 [get_ports CNT_VLD]
# set_property PACKAGE_PIN AB8 [get_ports sda]
# set_property PACKAGE_PIN Y8 [get_ports scl]
# set_property IOSTANDARD LVCMOS33 [get_ports CHIP_EN]
# set_property IOSTANDARD LVCMOS33 [get_ports CI_CTRL]
# set_property IOSTANDARD LVCMOS33 [get_ports CLK_OUT]
# set_property IOSTANDARD LVCMOS33 [get_ports CLK_TX]
# set_property IOSTANDARD LVCMOS33 [get_ports CNT_VLD]
# set_property IOSTANDARD LVCMOS33 [get_ports INT]
# set_property IOSTANDARD LVCMOS33 [get_ports scl]
# set_property IOSTANDARD LVCMOS33 [get_ports sda]
# set_property IOSTANDARD LVCMOS33 [get_ports TRIGGER]

#转接板
set_property PACKAGE_PIN P14 [get_ports {pixel_so_in[0]}]
set_property PACKAGE_PIN N13 [get_ports {pixel_so_in[1]}]
set_property PACKAGE_PIN W9 [get_ports {pixel_so_in[2]}]
set_property PACKAGE_PIN V8 [get_ports {pixel_so_in[3]}]
set_property PACKAGE_PIN AB7 [get_ports {pixel_so_in[4]}]
set_property PACKAGE_PIN AB6 [get_ports {pixel_so_in[5]}]
set_property PACKAGE_PIN AA8 [get_ports {pixel_so_in[6]}]
set_property PACKAGE_PIN Y7 [get_ports {pixel_so_in[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pixel_so_in[0]}]
set_property PACKAGE_PIN Y8 [get_ports CLK_OUT]
set_property PACKAGE_PIN AB8 [get_ports CHIP_EN]
set_property PACKAGE_PIN V7 [get_ports INT]
set_property PACKAGE_PIN U7 [get_ports CI_CTRL]
set_property PACKAGE_PIN Y9 [get_ports TRIGGER]
set_property PACKAGE_PIN V9 [get_ports CLK_TX]
set_property PACKAGE_PIN N14 [get_ports CNT_VLD]
set_property PACKAGE_PIN R14 [get_ports sda]
set_property PACKAGE_PIN R16 [get_ports scl]
set_property IOSTANDARD LVCMOS33 [get_ports CHIP_EN]
set_property IOSTANDARD LVCMOS33 [get_ports CI_CTRL]
set_property IOSTANDARD LVCMOS33 [get_ports CLK_OUT]
set_property IOSTANDARD LVCMOS33 [get_ports CLK_TX]
set_property IOSTANDARD LVCMOS33 [get_ports CNT_VLD]
set_property IOSTANDARD LVCMOS33 [get_ports INT]
set_property IOSTANDARD LVCMOS33 [get_ports scl]
set_property IOSTANDARD LVCMOS33 [get_ports sda]
set_property IOSTANDARD LVCMOS33 [get_ports TRIGGER]

#uart
set_property IOSTANDARD LVCMOS33 [get_ports rx]
set_property IOSTANDARD LVCMOS33 [get_ports tx]
set_property PACKAGE_PIN T6 [get_ports tx]
set_property PACKAGE_PIN U5 [get_ports rx]
# set_property PACKAGE_PIN G15 [get_ports tx]
# set_property PACKAGE_PIN H15 [get_ports rx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_led]
set_property PACKAGE_PIN R2 [get_ports uart_led]

set_property IOSTANDARD LVCMOS33 [get_ports ttl_signal]
set_property PACKAGE_PIN M16 [get_ports ttl_signal]

create_clock -period 20.000 -name sys_clk -waveform {0.000 10.000} [get_ports sys_clk]

create_generated_clock -name u_pcl7152_top/u_i2c_dri/dri_clk__0 -source [get_pins u_pcl7152_top/u_pcl7152_clk_wiz/inst/mmcm_adv_inst/CLKOUT0] -divide_by 4 [get_pins u_pcl7152_top/u_i2c_dri/dri_clk_reg/Q]




create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list u_pcl7152_top/u_pcl7152_clk_wiz/inst/clk_out3]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {datin_bram_w_data[0]} {datin_bram_w_data[1]} {datin_bram_w_data[2]} {datin_bram_w_data[3]} {datin_bram_w_data[4]} {datin_bram_w_data[5]} {datin_bram_w_data[6]} {datin_bram_w_data[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 11 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {datin_bram_w_addr[0]} {datin_bram_w_addr[1]} {datin_bram_w_addr[2]} {datin_bram_w_addr[3]} {datin_bram_w_addr[4]} {datin_bram_w_addr[5]} {datin_bram_w_addr[6]} {datin_bram_w_addr[7]} {datin_bram_w_addr[8]} {datin_bram_w_addr[9]} {datin_bram_w_addr[10]}]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets bram_clk]
